The present invention relates generally to transistors and, more particularly, to fin field effect transistors (FinFETs).
Scaling of device dimensions has been a primary factor driving improvements in integrated circuit performance and reduction in integrated circuit cost. Due to limitations associated with existing gate-oxide thicknesses and source/drain (S/D) junction depths, scaling of existing bulk MOSFET devices below the 0.1 xcexcm process generation may be difficult, if not impossible. New device structures and new materials, thus, are likely to be needed to improve FET performance.
Double-gate MOSFETs represent new devices that are candidates for succeeding existing planar MOSFETs. In double-gate MOSFETs, the use of two gates to control the channel significantly suppresses short-channel effects. A FinFET is one example of a recent double-gate structure that includes a channel formed in a vertical fin. The FinFET is similar to existing planar MOSFETs in layout and fabrication. The FinFET also provides a range of channel lengths, CMOS compatibility and large packing density compared to other double-gate structures.
Consistent with the present invention, methods for forming a FinFET gate are provided that alleviate problems that occur, using conventional gate formation processes, because of anti-reflective coating (ARC) over-etch due to high topography. During conventional ARC etching to form a FinFET gate, using, for example, CF4 or CHF3 etching processes, the underlying polysilicon gate material can be attacked, thus, increasing the chance of source/drain attack (e.g., rough or dirty fin sidewalls), pitting and poor profile. To alleviate this problem, an etch stop layer may be formed, consistent with the invention, between the ARC and the gate polysilicon. The etch stop layer prevents over-etching of the ARC, that may occur due to the severe topography of the Fin device, from attacking the source/drain regions or gate material of the FinFET. The etch stop layer may include Ti or TiN that has a very low etch rate in a fluorine etching process, such as, for example, a CF4/Ar etching process. Subsequent to etching of the ARC, the etch stop layer and polysilicon material of the gate may be etched using, for example, a Cl2/HBr etching process.
Additional advantages and other features of the invention will be set forth in part in the description which follows and, in part, will become apparent to those having ordinary skill in the art upon examination of the following, or may be learned from the practice of the invention. The advantages and features of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of forming a gate for a FinFET. The method includes forming a first layer of material over a fin and forming a second layer over the first layer, the second layer including at least one of Ti and TiN. The method further includes forming a third layer over the second layer, the third layer comprising an anti-reflective coating and etching the first, second and third layers to form the gate for the FinFET.
According to another aspect of the invention, a method of forming a gate electrode for a FinFET is provided. The method includes forming a first layer over a fin and forming an etch stop layer over the first layer. The method further includes applying an anti-reflective coating to the etch stop layer and forming a photo-resist layer in a gate pattern over the anti-relective coating. The method also includes etching the anti-reflective coating and etching the etch stop layer and the first layer to form the gate electrode in the first layer in a shape corresponding to the gate pattern.
According to a further aspect of the invention, a structure for forming a FinFET is provided. The structure includes a fin formed on a substrate and a first layer formed over the fin. The structure further includes a second layer formed over the first layer, the second layer including at least on of Ti and TiN. The structure also includes a third layer formed over the second layer, the third layer including an anti-reflective coating, and wherein the first, second and third layers are etched to form a gate for the FinFET in the first layer.
Other advantages and features of the present invention will become readily apparent to those skilled in this art from the following detailed description. The embodiments shown and described provide illustration of the best mode contemplated for carrying out the invention. The invention is capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings are to be regarded as illustrative in nature, and not as restrictive.